A plasma processing device for use in a manufacture of semiconductor includes a vacuum processing chamber capable of maintaining a vacuum state therein; a susceptor disposed within the chamber for mounting thereon an object to be processed, e.g., a semiconductor wafer (hereinafter simply referred to as a “wafer”); a gas supply unit for supplying a processing gas into the chamber; and a plasma generation unit for generating plasma in the chamber under the atmosphere of the processing gas of a predetermined vacuum level. The plasma generated by a high frequency power supplied from a high frequency power supply performs a plasma processing such as etching on the wafer placed on the susceptor.
The plasma generating unit includes an upper electrode (not shown) and a lower electrode disposed to face each other, wherein a susceptor 1 serves as the lower electrode and an electrostatic chuck is provided on a top surface of the susceptor, as shown in FIG. 4.
A focus ring 2 is disposed on a periphery of the susceptor 1 and serves to converge the plasma to the wafer w. There is a gap of about 1 mm between an outer periphery of the wafer W and an inner periphery of the focus ring 2.
Further, the focus ring 2 is surrounded by a cover ring 3 made of an insulating material. The cover ring 3 is supported on a base ring 4, which is fixed to the susceptor 1. Hereinafter, mainly a set containing a focus ring and a cover ring will be referred to as a ring mechanism.
Under such configuration, when processing the wafer W by generating the plasma, the plasma is concentrated at the wafer W by the focus ring 2 and an etching process or the like is performed on the wafer W. In such conventional ring mechanism, when the plasma is concentrated by the focus ring 2, the peripheral portion of the plasma reaches only a vicinity of the cover ring 3. As a result, the high frequency power (high frequency current) is mostly drawn into the wafer W and the focus ring 2, which in turn increases the electric potential difference therebetween. Since, however, the current does not always uniformly flow into the wafer W and the focus ring 2, there occurs a potential difference therebetween. As a result, an arc discharge occurs between the wafer W and the focus ring 2 as shown in FIG. 4, causing problems, e.g., damaging a circuit device formed on the wafer.
Such problem can be attributed to the gaps that exist between configuration parts disposed around the periphery of the susceptor. Further, according to the investigation undertaken by the applicants, it was proved that the structure of the cover ring has great influence on the occurrence of the arc discharge.
Further, a parallel plate type etching apparatus is well known among plasma processing devices for performing etching. As shown in FIG. 19, the etching apparatus includes a processing chamber 71 capable of maintaining a vacuum state therein, wherein the processing chamber 71 has therein a susceptor 72 also serving as a lower electrode. An upper electrode 76 is installed to face a loading surface of the susceptor 72 with a space defined as a processing space provided therebetween. The upper electrode 76 further serves as a gas supply unit for supplying a processing gas from a gas supply system (not shown) into the processing chamber. The processing chamber is evacuated via a gas exhaust line 73 by a vacuum pump system (not shown), thereby forming a vacuum state therein.
Provided on the outer periphery of the susceptor 72 are a focus ring (inner ring) 74 surrounding a loaded wafer W; and a cover ring (outer ring) 75 for fixing the focus ring 74. The focus ring 74 is made of a conductive or semiconductive material and the cover ring 75 is formed of an insulating material, e.g., quartz (SiO2). The ring mechanism serves to converge plasma at the wafer W while increasing uniformity of etching rate. As shown in FIG. 20, the focus ring 74 is of a protruded shape, wherein an inner side of the top surface thereof forms a step 77 lowered by a thickness of the wafer W and an outer side of the top surface thereof forms a step 78 lowered by a thickness of a pressurizing click portion of the cover ring 75. By this configuration, the top surface of the wafer W, the top surfaces of the focus ring 74 and the cover ring 75 are set to be on a same horizontal plane.
Further, an outer end side of the cover ring 75 is tapered, thereby serving to provide uniform flow of exhaust gas or increase uniformity in the plasma. Further, in case the cover ring 75 is formed of quartz, oxygen radicals generated in etching the quartz act during parts of the etching process of the wafer W.
When using the focus ring 74 described above, the etching rate of a peripheral region (region in a vicinity of an outer end portion) of the wafer W is varied. In general, in case of processing a wafer W having a size of 8 inches, a focus ring 74 with a width of, e.g., about 30 mm, and a thickness of 6.5 mm is employed. In such a case, the etching rate tends to rapidly decrease at first and then sharply increase at the peripheral region of the wafer W, as shown in FIG. 21. The region showing such a great change is within about 10 mm from the peripheral portion of the wafer W.
Thus, when processing the wafer W on which a resist mask is formed, with the etching rate greatly increasing at the outer peripheral region of the wafer, an opening of the resist mask is enlarged compared with a central portion of the wafer. As a result, a line width of the outer peripheral region of the wafer becomes larger than that of the central region in a wiring formed by the etching, though the resist mask has originally the same line widths, so that uniformity in line widths over the entire surface of the wafer is deteriorated.
Furthermore, since the resist mask is coated with a uniform thickness by a spin coating method, the resist mask is removed faster at the outer peripheral region of the wafer than at a central region thereof, and thus thinned out. That is, since the resist mask on the outer peripheral region is removed during the processing, there is likelihood of an exposure of a surface covered by the mask.
Thus, by not being able to place a device at the peripheral side of the wafer W, a yield is lowered. Further, since pressure variation of the atmosphere of the plasma processing gas significantly influences the etching rate of the peripheral region of the wafer W, a tolerance of the pressure variation is reduced. Therefore, control of the etching rate by way of varying the pressure of the processing gas is difficult to achieve.